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CS 572 Micro ArchitectureFall 2017MW 14:00-15:15, ENS-106 San Diego State University
Instructor: Dr. Tao Xie GMCS 535, 619-594-2014 Office hours: MW 11 am - 12 pm, or by appointment. |
Date |
Topics |
Reading Assignments |
Slides |
8/28/17 |
Introduction |
Ch 1.1-1.6 |
|
8/30/17 |
Performance Measurement |
Ch 1.8-1.9 |
|
9/06/17 |
Instruction Set Architecture |
B.1-B.3, B.4, B.5 |
|
9/11/17 |
Instruction Set Architecture: MIPS1 |
B.6, B.7, B.9 |
|
9/13/17 |
Instruction Set Architecture: MIPS2 |
|
|
9/18/17 |
Single-Cycle Processor Implementation1 |
|
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9/20/17 |
Single-Cycle Processor Implementation2 |
|
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9/25/17 |
Multi-Cycle Processor Implementation 1 |
|
|
9/27/17 |
Multi-Cycle Processor Implementation 2 |
|
|
10/02/17 |
Pipeline: Introduction |
A.1 |
|
10/04/17 |
Pipeline: Structural Hazards |
A.2 |
|
10/09/17 |
Pipeline: Data Hazards |
A.3 |
|
10/11/17 |
Pipeline: Branch Prediction |
A.3 |
|
10/16/17 |
Exercise Class |
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|
10/18/17 |
Review session for midterm exam |
The Study Guide for the Midterm exam |
|
10/23/17 |
Midterm |
|
|
10/25/17 |
Midterm Summary Session |
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|
10/30/17 |
Pipeline: Exceptions, control |
A.4 |
|
11/01/17 |
Instruction-level parallelism: Introduction |
Ch2.1 |
|
11/06/17 |
Instruction-level parallelism: Scoreboard |
A.7 |
|
11/08/17 |
Tomasulo’s Algorithm: Introduction and Example |
Ch2.4-Ch2.5 |
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11/13/17 |
Tomasulo’s Algorithm: A loop example |
Ch2.5 |
|
11/15/17 |
Tomasulo’s Algorithm: Reorder Buffer |
Ch2.6 |
|
11/20/17 |
Memory Hierarchy: Set Associative Cache |
Ch5.1-Ch5.2 |
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11/27/17 |
Memory Hierarchy: Cache Performance |
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|
11/29/17 |
Final Exam Preview |
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|
12/04/17 |
Flash Memory Based SSDs in Mobile Storage Systems |
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Monday, Dec. 18 |
Final Exam (13:00 - 15:00) |
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