San Diego State University

Department of Computer Science

 

 CS 370 Computer Architecture Fall 2017

 

 

Class Web Page:        

The class web page is located at http://taoxie.sdsu.edu/cs370/index.html. This page contains course announcements, syllabus, and other information.

 

Class Location and Time:        

Music-120; MW 4 pm - 5:15 pm

 

Instructor:           

Tao Xie, Ph.D.

Office hours:         Monday&Wednesday: 11 am - noon or by appointment

Office:                    GMCS 535, Office Phone 619-594-2014

Email: txie@mail.sdsu.edu

Computer Achitecture and System Lab: http://casl.sdsu.edu

 

Graders:           

Tony La

Email: tonyla858@gmail.com

Office: GMCS 401

Office hours: Monday & Wednesday 12 PM ~ 1:45 PM; Thursday 2 PM ~ 3:30 PM.

 

Course Description:        

Logic gates, combinational circuits, sequential circuits, memory and bus system, control unit, CPU, exception processing, traps and interrupts, input-output and communication, reduced instruction set computers, use of simulators for analysis and design of computer circuits, and traps/interrupts.

 

Textbook:             

Mano, M. Morris, and Kime, Charles R., Logic and Computer Design Fundamentals, 5th Ed, Pearson, 2015.


Class Schedule             


Lecture-1 Slides             

Lecture-2 Slides             

Lecture-3 Slides             

Lecture-4 Slides             

Lecture-5 Slides             

Lecture-6 Slides             

Lecture-7 Slides             

Lecture-8 Slides             

 

Course Objectives:

1.  To learn fundamentals of digital systems analysis and design.

2.  To become familiar with components and functional units used in digital computers.

3.  To obtain a rudimentary understanding of computer organization and architecture.

4.  To acquire some knowledge of the PC hardware and associated peripherals.

 

Prerequisites:

1.  CS 237 - Machine Organization.

2.  Assembly Language Knowledge of the MC68000 assembly language.

 

Course Topics* and Allocated Time:

1.   Introduction (1/2 week)

About the subject, Levels of abstraction of digital systems (transistor, gate, register, processor). Design and analysis of digital systems. CAD tools

 

2.   Data types and representation (1 week)

Binary coding and conversions between different number systems. Ones, two's complement, sign magnitude representation. Adding, subtracting and multiplication of binary numbers. Fixed and floating-point representation. Error detection and correction (cube representation of binary strings, Hamming code)

 

3.   Boolean algebra and logic design (2 weeks)

Axiomatic definition of Boolean algebra. Boolean operators and duality principle Theorems of Boolean algebra. Boolean functions and expression equivalence Minterms and maxterms (standard forms of Boolean functions). Sixteen binary logic operations . Digital logic gates and example of full-adder . Design with NAND/NOR gates, complex gates. Castom design (gate arrays, FPGA)

 

4.   Simplification of Boolean functions (1&1/2 weeks)

Karnuagh maps (1,2,3, 4 and 5 Cvariable maps). Selection of prime implicants. Don't care conditions. Technology mapping for gate arrays (standard to NANMD/NOR schemes, standard to gate arrays. Timing issues. Static and dynamic hazard.

 

5.   Combinational circuit analysis and design (2 weeks)

Ripple-carry serial adder. Carry-look-ahead generator. CLA adder. Twos' complement adder subtractor. Arithmetic-logic unit. Decoders . Multiplexers. Priority encoders. Magnitude comparators. Shifters (including barrel shifters). ROM. Programmable logic arrays. Full adder with ROM, PLA

 

6.   Sequential circuit analysis and design (2 weeks)

SR-latch (NOR, NAND implementation). Gated SR-latch, Gated D-latch. Flip-flops. Master-slave FF, Edge triggered FF. FF types (SR, JK, D, T). Design of sequential circuits (analysis and synthesis with state tables). Shift registers. Serial adders. Counters (ripple, synchronous).

 

7.   Memory organization (1 week)

Simple RAM (coincident decoding). Array of RAM chips (extending the address space and the word size). Push-down stack. FIFO queue. Memory timing . Implementation of error detection and correction. ROM.

 

8.   Processor (2 weeks)

Register transfer micro operations . Register transfer language. Arithmetic micro operations. Logic micro operations. ALU and shifter unit. Datapaths. Bus transfer Processor unit . Control unit (hardwired and micro programmed). Micro programs and micro routines. Instruction set and addressing modes. Complex instruction set vs. RISC. Reduced instruction set C a 32-bit example. Data-forwarding and branch prediction.

 

9.   System bus (2 weeks)

Synchronous bus control. Asynchronous bus control. Connecting memory to CPU Implementation of interrupts. Vectored interrupts and autovectored interrupts. Programming with traps and interrupts

 

*  Topics OUT of Chapter 1 to Chapter 10 will NOT be included in our assignments and exams.

 

Assignment Due Days and Test Days:

Homework Assignment#1 (5%, due in class on Wednesday September 27) 

Homework Assignment#1 Text 

Lab Assignment#1 (5%, due by 11:59 pm on September 22 Friday) 

 

Evaluation:

1.  Test1 75-minute close book & in class ...20%

2.  Test2 75-minute close book & in class ...20%

3.  Homework assignment1 ~ Homework assignment3 ...15% total (each homeowrk assignment 5%)

4.  Lab assignment1 ~ Lab assignment3 ...20% total (Lab1-5%; Lab2-7%; Lab3-8%)

5.  Final exam ...25%

6.  Weekly exercises* ...0%

*   Each weekly exercise consists of several questions and will be given to you every week. These weekly exercises will NOT be graded and will contribute ZERO to your final grade. However, they will make you feel comfortable when you take tests and final exam. Solutions to these exercises will be posted on our class web page and you are highly recommended to self-evaluate your weekly exercises.

 

Relationship to Other Courses:

This course is the first course in a series of courses in computer architecture.  It prepares you for courses such as CS570 (Operating systems), CS572 (Microprocessor Architecture), and CS674 (Advance Computer Architecture).

 

Class Guidelines:

 

 

 

Grading Policy:

          100       90        86        82        78         74        70        66        62          58         54         50        0

     |     A    |   A-    |    B+   |    B    |     B-    |   C+   |    C     |    C-   |    D+    |     D    |    D-    |    F    |

 

References:         

1.  Carter, J. W., Digital Designing with Programmable Logic Devices.

2.  Clements, A., Principle of Computer Hardware.

3.  Daniels, J., Digital Design from Zero to One.

4.  Dietmeyer, D. L., Logic Design of Digital Systems, 3rd Ed.

5.  Dewey, A., Analysis and Design of Digital Systems with VHDL.

6.  Katz, R. H., Contemporary Logic Design.

7.  Kline, R. M., Structured Digital Design.

8.  Lewin, M. H., Logic Design and Computer Organization.

9.  Marino, L. R., Principles of Computer Design.

10. McCalla, T. R., Digital Logic and Computer Design.

11. Pappas, N. L., Digital Design.

12. Pucknell, D. A., Fundamentals of Digital Logic Design.

13. Roth, D. A., Fundamentals of Logic Design, 4th Ed.

14. Sandige,  R.  S.,  Digital Concepts Using Standard Integrate Circuits.

15. Tinder, R. F., Digital Engineering Design - A Modern Approach.

16. Wakerly, J. F., Digital Design Principles and Practices.

17. Wong, D. G., Digital Systems Design.