Department of Computer
Science

** CS 370 Computer
Architecture Fall 2017**

__Class
Web Page:__

The class web page is located at http://taoxie.sdsu.edu/cs370/index.html. This page contains course announcements, syllabus, and other information.

__Class
Location and Time:__

Music-120; MW 4 pm - 5:15 pm

__Instructor:__

Tao Xie,
Ph.D.

Office
hours:
Monday&Wednesday: 11 am - noon or by appointment

Office:
GMCS 535, Office Phone 619-594-2014

Email: txie@mail.sdsu.edu

Computer Achitecture and System Lab:
http://casl.sdsu.edu

__Graders:__

Tony La

Email: tonyla858@gmail.com

Office: Monday & Wednesday GMCS 425; Thursday GMCS 422

Office hours: Monday & Wednesday 12 PM ~ 1:45 PM; Thursday 2 PM ~ 3:30 PM.

__Course
Description:__

Logic gates, combinational circuits, sequential circuits, memory and bus system, control unit, CPU, exception processing, traps and interrupts, input-output and communication, reduced instruction set computers, use of simulators for analysis and design of computer circuits, and traps/interrupts.

__Textbook:__

Mano, M. Morris, and Kime, Charles R., Logic and Computer Design Fundamentals,
**5th Ed**, Pearson, 2015.

__Course
Objectives:__

1. To learn fundamentals of digital systems
analysis and design.

2. To become familiar with components and
functional units used in digital computers.

3. To obtain a rudimentary understanding of
computer organization and architecture.

4. To acquire some knowledge of the PC
hardware and associated peripherals.

__Prerequisites:__

1. CS 237 - Machine Organization.

2. Assembly Language Knowledge of the
MC68000 assembly language.

__Course
Topics* and Allocated Time:__

1. Introduction (1/2
week)

About the subject, Levels of abstraction of digital systems (transistor, gate, register, processor). Design and analysis of digital systems. CAD tools

2. Data types and representation (1
week)

Binary coding and conversions between different number systems. Ones, two's complement, sign magnitude representation. Adding, subtracting and multiplication of binary numbers. Fixed and floating-point representation. Error detection and correction (cube representation of binary strings, Hamming code)

3. Boolean algebra and logic design (2 weeks)

Axiomatic definition of Boolean algebra. Boolean operators and duality principle Theorems of Boolean algebra. Boolean functions and expression equivalence Minterms and maxterms (standard forms of Boolean functions). Sixteen binary logic operations . Digital logic gates and example of full-adder . Design with NAND/NOR gates, complex gates. Castom design (gate arrays, FPGA)

4. Simplification of Boolean
functions (1&1/2 weeks)

Karnuagh maps (1,2,3, 4 and 5 ¨Cvariable maps). Selection of prime implicants. Don't care conditions. Technology mapping for gate arrays (standard to NANMD/NOR schemes, standard to gate arrays. Timing issues. Static and dynamic hazard.

5. Combinational circuit analysis and
design (2 weeks)

Ripple-carry serial adder. Carry-look-ahead generator. CLA adder. Twos' complement adder subtractor. Arithmetic-logic unit. Decoders . Multiplexers. Priority encoders. Magnitude comparators. Shifters (including barrel shifters). ROM. Programmable logic arrays. Full adder with ROM, PLA

6. Sequential circuit analysis and
design (2 weeks)

SR-latch (NOR, NAND implementation). Gated SR-latch, Gated D-latch. Flip-flops. Master-slave FF, Edge triggered FF. FF types (SR, JK, D, T). Design of sequential circuits (analysis and synthesis with state tables). Shift registers. Serial adders. Counters (ripple, synchronous).

7. Memory organization (1
week)

Simple RAM (coincident decoding). Array of RAM chips (extending the address space and the word size). Push-down stack. FIFO queue. Memory timing . Implementation of error detection and correction. ROM.

8. Processor (2
weeks)

Register transfer micro operations . Register transfer language. Arithmetic micro operations. Logic micro operations. ALU and shifter unit. Datapaths. Bus transfer Processor unit . Control unit (hardwired and micro programmed). Micro programs and micro routines. Instruction set and addressing modes. Complex instruction set vs. RISC. Reduced instruction set ¨C a 32-bit example. Data-forwarding and branch prediction.

9. System bus (2 weeks)

Synchronous bus control. Asynchronous bus control. Connecting memory to CPU Implementation of interrupts. Vectored interrupts and autovectored interrupts. Programming with traps and interrupts

*
Topics OUT of Chapter 1 to Chapter 10 will NOT be included in our
assignments and exams.

__Assignment Due Days and Test Days:__

Homework Assignment#3 (due in class on December 4)

Lab Assignment#3 (10%, due by 11:59pm on Nov. 30 Thursday)

__Evaluation:__

1. Test1 75-minute close book & in class ...20%

2. Test2 75-minute close book & in class ...20%

3. Homework assignment1 ~ Homework assignment3 ...15% total (each homeowrk assignment 5%)

4. Lab assignment1 ~ Lab assignment3 ...20% total (Lab1-5%; Lab2-7%; Lab3-8%)

5. Final exam ...25%

6. Weekly exercises* ...0%

* Each weekly exercise consists of several questions and will be given to you every week. These weekly exercises will NOT be graded and will contribute ZERO to your final grade. However, they will make you feel comfortable when you take tests and final exam. Solutions to these exercises will be posted on our class web page and you are highly recommended to self-evaluate your weekly exercises.

__Relationship to Other
Courses:__

This course
is the first course in a series of courses in computer architecture. It prepares you for courses such as
CS570 (Operating systems), CS572 (Microprocessor Architecture), and CS674
(Advance Computer Architecture).

__Class
Guidelines:__

**Prerequisite:**The prerequisite for this course is CS237. This prerequisite will be strictly enforced. All registered students are required to bring me the proof of having passed CS237, or an equivalent course. Those who fail to provide this proof will be given a grade of ¡°F¡± in the class.- There will be
**NO****make-up tests**without a verified excuse. **I will not sign late drop slips!**By enrolling in this course, you are making a commitment to finish it. If there is any uncertainty about your future enrolment status beyond Feburary 4, 2014, you should drop the course now. By staying in class and dropping out later, you are taking away a seat from the many people who need to crash the class this semester in order to graduate this year.- The
**final exam**is scheduled on Monday, December 18, 2017, 15:30-17:30. Failure to appear for the final exam will result in a grade of F in the course, unless you make prior arrangements with me for an Incomplete (see the requirements for receiving and Incomplete below). If you cannot attend the final exam for any reason (conflict with another course, work schedule, etc.), you should drop this class now.**No make-up final exam**will be given. **Incompletes:**To receive a grade of Incomplete in this class, you must meet all of the following criteria: a. You must have extenuating circumstances beyond your control for not completing the course, and I will be the sole judge as to whether the circumstances warrant withdrawal from the class. Official verification is required to corroborate your circumstances. b. You must have completed Test#1, Test#2, and at least 2 assignments. c. You must have a grade of C or better in all coursework completed thus far. Note that this means a C or better in every test and every assignment.- There will be
**NO extra credit**in any assignments, tests, and final exam. - All homeworks are due at the
start of class on the indicated due day. If you can not make it to the class,
please ask your friend to bring it at the start of class.
**No late homework will be accepted. No late lab assignment will be accepted.** - All the exams are
**close-book, close-notes**. You can only bring one piece of paper (size A4, one side) as a "cheating sheet" for each of the three exams. Note that NO solutions to ANY questions including homework and text example questions are allowed on your "cheating sheet"! - Any questions about grading must be brought to the
attention of the grader or the instructor
**within one week**after the item in question is returned. Your request must include a short written statement describing your question or concern. **No cell phones**,**No Pagers**,**No speaking**in class.**Cheating:**Any one caught cheating/collaborating on an exam or any assignment will receive zero for that assignment or exam. If a student is caught twice, he/she will receive an F in the course and the incident will be reported to the Office of Judicial Affairs for disciplinary proceedings. Note: If, for instance, you allow your assignment be copied by a classmate, you are considered as guilty as the copier.**The instructor reserve the right to revises the Class Guidelines when he thinks that it is necessary to do so.**

__Grading
Policy:__

100
90
86
82
78
74
70
66
62
58
54
50
0

** **| A | A- | B+ | B | B- | C+ | C | C- | D+ | D | D- | F |

__References:
__

1. Carter, J. W., Digital Designing with
Programmable Logic Devices.

2. Clements, A., Principle of Computer
Hardware.

3. Daniels, J., Digital Design from Zero to
One.

4. Dietmeyer, D.
L., Logic Design of Digital Systems, 3rd Ed.

5. Dewey, A., Analysis and Design of
Digital Systems with VHDL.

6. Katz, R. H., Contemporary Logic Design.

7. Kline, R. M., Structured Digital
Design.

8. Lewin, M. H.,
Logic Design and Computer Organization.

9. Marino, L. R., Principles of Computer
Design.

10. McCalla, T. R., Digital Logic and Computer
Design.

11. Pappas,
N. L., Digital Design.

12. Pucknell, D. A., Fundamentals of Digital Logic
Design.

13. Roth, D.
A., Fundamentals of Logic Design, 4th Ed.

14. Sandige, R. S., Digital Concepts Using Standard
Integrate Circuits.

15. Tinder,
R. F., Digital Engineering Design - A Modern Approach.

16. Wakerly, J. F., Digital Design Principles and
Practices.

17. Wong, D.
G., Digital Systems Design.