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The midterm exam will occur on Monday, Oct. 23. This exam is closed book and
closed notes. The exam is worth 20% of your final grade.
Although a calculator is not necessary to complete the exam, you may bring a calculator
with you. Please do not bring a laptop with sensitive information on computer architectures.
A list of general
advice about studying for the exam is to aim for understanding over
memorization. 1.
Study the quizzes we have taken. 2.
Go through the written assignments. 3.
Review the course notes to see what was emphasized in the lectures. 4. You should be familiar with the core set of instructions, their use, the three types of
formats. In what follows, you will find a guide of topics
that may be covered in the midterm exam. Note that questions
pertaining to any of these topics may appear on the midterm exam.
- Technology trends
- Performance
- Cost
- Moore's law
- What is computer architecture?
- Computer engineering methodology
- Performance measurement
- Performance metrics: response time, throughput
- Measuring CPU time
- Amdahl's law
- Classifying instruction set architectures
- Accumulator
- Stack
- General purpose register
- Load/Store
- Memory/Memory
- Memory Addressing
- Endianess and Alignment
- Types of addressing modes
- Types of instructions
- Instruction formats
- Types of operations
- MIPS - A case study of ISA
- MIPS design principles
- MIPS registers and memory addressing
- MIPS core instructions: branching using slt and bne or beq;
load-store architecture
- Binary representation - Branch and Jump
- How to decode?
- Single-cycle processor implementation
- Processor design: general rules
- Review digital design
- Datapath for instruction fetch
- Datapath for R-type instructions
- Datapath for Load/Store
- Datapath for branch
- Critical paths
- Single-cycle processor: Controller
- Control unit design: combinational logic
- Determine control points
- Control unit structure
- ALU control: Truth table
- Control unit implementation
- Multicycle processor implementation
- Motivation
- Key idea: one cycle for each major tasks (IF, ID, EX, MEM, WB)
- Multicycle design
- Multicycle execution: actions for R-type and memory-reference
instructions; actions for branches and jumps
- Full multicycle implementation
- Pipelining Overview
- What is pipelining?
- Throughput vs. latency
- Pipelining a processor: 5 steps (IF, ID, EX, MEM, WB)
- Basic pipeline for MIPS
- Speedup equations for pipelining
- Pipelining: Structural Hazards
- What are structural hazards
- One memory port structural hazard
- Common structural hazard
- Solutions?
- Pipelining: Data Hazards
- What are data hazards?
- Read After Write (RAW)
- Data hazard detection
- Data hazard - stalling
- Data hazard - forwarding
- Pipelining: Control or Branch Hazards
- What are control hazards?
- Reducing branch delay
- Control hazard solutions
- Branch behavior in programs
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